The present invention generally relates to a power supply system for electronic devices, and more particularly, to a circuit for limiting the inrush current to a power source.
A typical power supply system includes a large electrolytic capacitor to develop a DC voltage from a fully rectified AC voltage. This large capacitor appears to be a short initially and a large inrush current is drawn from the AC source. This inrush current is limited by the line impedance and the circuit series impedance. The lower impedance in series, the higher the peak current. The inrush current will decay exponentially until it becomes zero, when the capacitor voltage becomes equal to the peak value.
Almost all of the power supply designs incorporate some sort of inrush current limiting means. The most economical way is to use an NTC thermister which has a very high impedance initially and drops to one-tenth of its value when it becomes hot during operation of the power supply. Other inrush limiting designs include a series resistance bypassed by a relay. Some designs incorporate a TRIAC or an SCR in place of a relay contactor. The relay contactor, due to its electromechanical feature, is unreliable while the SCR or the TRIAC used in series with the line are very inefficient and complex.
FIG. 1 shows an existing power supply circuit configuration 100. The circuit configuration 100 comprises a power input 101 coupled to a rectifier 102 wherein the rectifier 102 is coupled to a bypass resistor 108. The bypass resistor 108 is coupled to a relay 104 and an inductor 112. The configuration further includes an auxiliary bias 110 wherein the auxiliary bias 110 is coupled to a boost output 128.
The circuit configuration 100 includes a boost regulator power source and a circuit for limiting an inrush current 103. The rectifier bridge 102, the inductor 112, diodes 116, 122, transistor 122, capacitor 124 and pulse width modulator 126 form the boost regulator power source and boost an input AC voltage from approximately 117 volts AC, for example, to approximately 400 volts DC. Capacitor 114 is a high frequency bypass capacitor. Diode 116 is a bypass diode used to prevent saturation of the boost inductor 112. The relay 104, the resistor 108 and the auxiliary bias 110 form the circuit for limiting the inrush current.
Circuit Operation
At the first turn on of the power input 101, the relay 104 is open (contact 9 is connected with contact 10) and the bypass resistor 108 limits the current flowing through diode 116 and capacitor 114. By the time the auxiliary bias 110 reaches a voltage level required to close the relay 104 (contact 8 with contact 9), the voltage across the capacitor 114 will be equal to the AC peak voltage and the inrush current will drop to its minimal value.
However, during short outages of the power (e.g. during a brown out), the relay 104 stays on for a short period of time (e.g. 25-30 ms). As a result, if the power returns during this time, the capacitor 114 will experience a large inrush current. Additionally, the relay 104 requires an undesirably complicated and/or sensitive sensing and control circuit to turn it on and off.
Therefore, what is needed is an improved circuit for limiting inrush current in a power supply system. The circuit should be simple, cost effective and capable of being easily adapted to current technology. The present invention addresses such a need.
A circuit for limiting inrush current to a power source is disclosed. The circuit comprises a low voltage drop semiconductor device coupled to the power source and a resistor coupled in parallel with the low voltage drop semiconductor device. This circuit includes a diode coupled in parallel with the resistor and an AC detector coupled to the low voltage drop semiconductor device. The AC detector controls the low voltage drop semiconductor device in a manner such that when power is applied to the power source the inrush current to the power source is minimized.
Through the use of the present invention a low voltage drop semiconductor device is utilized in conjunction with an AC detector to simultaneously reduce transistor power dissipation and reduce the detrimental effects of inrush current. By reducing the transistor power dissipation as well as the detrimental effects of inrush current, a significant improvement in the overall efficiency of the circuit is achieved.